Analog IC Group (in the middle of nowhere:))

...faced with several ways to configure a basic circuit, in meeting some performance challenge, it often pays to use the simplest possible form. Of course, (if) you can't create new circuit forms, from scratch, in this way, only choose from pre-existing possibilities. The origination of topology is a daunting aspect of analog design, and the chief reason why many find it Difficult...        -- Barrie Gilbert

Research Interests:

• Integrated Circuits

• VLSI Signal Processing

• Device Modeling and CAD

• Wire-line and Wireless Communications

To applicants:  In general, I ONLY take grad students who have serious intention to pursue a PhD degree with me. Please stop emailing me for temporary internship positions or if you just want to get an MS degree for a job. Thanks.

Administrative Assistant:

Carolyn Genzel, 418 CSL, (217) 333-4847, genzel@uiuc.edu

Courses and Seminars:

• SP 2008: ECE 483 - Analog Integrated Circuit Design

• FA 2007: ECE 442 - Electronic Circuits

• SP 2007: ECE 483 - Analog Integrated Circuit Design

• FA 2006: ECE 598YC - Advanced Topics in Analog IC Design

• SP 2006: ECE 483 - Analog Integrated Circuit Design

• FA 2005: ECE 598YC - CMOS A-D Interface Circuits

• SP 2005: ECE 483 - Analog Integrated Circuit Design

• SP 2005: IC Seminar

Biography:

Yun Chiu received the B.S. degree in Physics from University of Science and Technology of China, the M.S. degree in EE from UCLA, and the Ph.D. degree in EECS from University of California at Berkeley. He was a senior staff member at CondorVision Technology Inc. (later PixArt Technology Inc.) between 1997 and 1999. In 2004, he joined the Department of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign, where he is now an assistant professor.

Dr. Chiu was a recipient of the Cal View Teaching Fellow Award, the Regents' Fellowship, the Intel Ph.D. Fellowship at Berkeley, the Foreign Scholar Award at UCLA, and the Outstanding Overseas Student Award from China's Ministry of Education. In 2004, he received the Jack Kilby Award from the International Solid-State Circuits Conference (ISSCC). In 2006, he also received the Chunhui Award for Foreign Visiting Scholars from China's Ministry of Education. He is an IEEE member and an Associate Editor of the IEEE Transactions on Circuits and Systems II: Express Briefs. He is also currently a member of the Technical Program Committees of the IEEE Custom Integrated Circuits Conference (CICC), the IEEE Asian Solid-State Circuits Conference (A-SSCC), and the IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT). He holds one U.S. patent.

Publications:

  Book:

1. Y. Chiu, Analysis and Design of Pipeline Analog-to-Digital Converters, Springer-Verlag, TBP. ISBN: 0387270396.

  Conference Papers:

2. (Invited) Y. Chiu, "Recent Advances in CMOS Data Conversion Circuits," to appear in the 9th IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'08), Beijing, China, 2008.

3. D. H. Kwon and Y. Chiu, "Efficiency and Linearity Enhancement of CMOS RF Power Amplifiers using Adaptive Baseband Digital Predistortion," to appear in IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT'08), Hsinchu, Taiwan, 2008.

4. R. Tseng, A. S. Poon, and Y. Chiu, "A mixed-signal MIMO beamforming receiver", in IEEE Radio and Wireless Symposium, RWS'08, Orlando, FL, 2008.

5. P. Bhoraskar and Y. Chiu, "A 6.1-mW dual-loop digital DLL with 4.6-ps rms jitter using window-based phase detector," in IEEE Asian Solid-State Circuits Conference, A-SSCC'07, Jeju, Korea, 2007.

6. W. Liu and Y. Chiu, "An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters," in the 7th IEEE International Conference on ASIC, ASICON'07, Guilin, China, 2007.

7. P. Huang and Y. Chiu, "A gradient-based digital algorithm for sampling clock skew calibration of SHA-less pipeline ADCs," in IEEE International Symposium on Circuits and Systems, ISCAS'07, New Orleans, LA, 2007.

8. B. Tsang, Y. Chiu, and B. Nikolic, "A 1.2V, 10.8mW, 500kHz DS modulator with 84dB SNDR and 96dB SFDR," in IEEE Symposium on VLSI Circuits, VLSI'06, Honolulu, Hawaii, 2006.

9. (Invited) Y. Chiu, B. Nikolic, and P. R. Gray, "Scaling of analog-to-digital converters into ultra-deep-submicron CMOS," in IEEE Custom Integrated Circuits Conference, CICC'05, San Jose, CA, 2005.

10. Y. Chiu, P. R. Gray, and B. Nikolic, "A 1.8V 14b 10MS/s pipelined ADC in 0.18mm CMOS with 99dB SFDR," in IEEE International Solid-State Circuits Conference, ISSCC'04, San Francisco, CA, 2004.

 Recipient of the ISSCC'04 Jack Kilby Award

11. Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband linearization of externally modulated fiber-optic links," in IEEE International Topical Meeting on Microwave Photonics, MWP'98, Princeton, NJ, 1998.

  Journal Articles:

12. R. Tseng, A. S. Poon, and Y. Chiu, "A mixed-signal vector modulator for eigen-beamforming receivers," to appear in IEEE Transactions on Circuits and Systems II: Express Briefs.

13. Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE Journal of Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004.

14. Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, "Least-mean-square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Transactions on Circuits and Systems I, special issue of Advances on Analog-to-Digital and Digital-to-Analog Converters, vol. 51, pp. 38-46, Jan. 2004.

15. Y. Chiu, "Inherently linear capacitor error-averaging techniques for pipelined A/D conversion," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 229-232, March 2000.

16. Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband electronic linearizer for externally modulated analog fiber-optic links," IEEE Journal of Photonics Technology Letters, vol. 11, pp. 48-50, Jan. 1999.

  Invited Conference and Workshop Tutorials/Presentations:

17. Tutorial Speaker, the 7th IEEE International Conference on ASIC (ASICON'07), 2007

18. Speaker, the Illinois Wireless Systems Symposium (ICWS) and the ICWS Circuits Area Open Forum, 2007

19. Speaker, DARPA/MTO TEAM Final PI Review, 2007

20. Short Course Instructor, workshops of the 2007 International Microwave Symposium (IMS'07)

21. Tutorial Speaker, 2006 IEEE Asian Solid-State Circuits Conference (A-SSCC'06)

22. Short Course Instructor, 2006 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT'06)

  Conferences, Workshops, and Seminars Organized/Chaired:

23. Session co-chair, 2008 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-DAT'08)

24. Co-organizer of the Circuits Area Open Forum of the Illinois Wireless Systems Symposium (ICWS), 2007

25. Session co-chair, the 7th IEEE International Conference on ASIC (ASICON'07), 2007

26. Co-organizer and chair of the Illinois Wireless Systems Symposium (ICWS) Seminar, 2007

27. Session co-chair, 2006 IEEE Custom Integrated Circuits Conference (CICC'06)

28. Session co-chair, 2006 IEEE Asian Solid-State Circuits Conference (A-SSCC'06)

29. Session chair, 2006 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-DAT'06)

30. Co-organizer and chair of the Graduate Seminar of the ECE Department, UIUC, 2005

31. Organizer and chair of the Integrated-Circuit Seminar of the Coordinated Science Lab, UIUC, 2005

Patent:

1. Y. Chiu, "Improved CMOS gain-boosting scheme using pole-isolation technique," U.S. patent No. 6,177,838.

©  Last modified: 02/15/08