Analog IC Group ( in the middle of nowhere :) )

...faced with several ways to configure a basic circuit, in meeting some performance challenge, it often pays to use the simplest possible form. Of course, (if) we can't create new circuit forms, from scratch, in this way, only choose from pre-existing possibilities. The origination of topology is a daunting aspect of analog design, and the chief reason why many find it difficult... -- Barrie Gilbert

Research Interests:

• Integrated Circuits

• VLSI Signal Processing

• Device Modeling and CAD

• Wire-line and Wireless Communications

To applicants:  In general, I ONLY take grad students who have serious intention to pursue a PhD degree with me. Please stop emailing me for temporary internship positions or if you just want to get an MS degree for a job. Thanks.

Administrative Assistant:

Carolyn Genzel, 418 CSL, (217) 333-4847, genzel@illinois.edu

Courses and Seminars:

• SP 2009: ECE 483 - Analog Integrated Circuit Design

• FA 2008: ECE 442 - Electronic Circuits

• SP 2008: ECE 483 - Analog Integrated Circuit Design

• FA 2007: ECE 442 - Electronic Circuits

• SP 2007: ECE 483 - Analog Integrated Circuit Design

• FA 2006: ECE 598YC - Advanced Topics in Analog IC Design

• SP 2006: ECE 483 - Analog Integrated Circuit Design

• FA 2005: ECE 598YC - CMOS A-D Interface Circuits

• SP 2005: ECE 483 - Analog Integrated Circuit Design

• SP 2005: IC Seminar

Biography:

Yun Chiu received the B.S. degree in Physics from University of Science and Technology of China, the M.S. degree in EE from UCLA, and the Ph.D. degree in EECS from University of California at Berkeley. He was a senior staff member at CondorVision Technology Inc. (later PixArt Technology Inc.) between 1997 and 1999. In 2004, he joined the Department of Electrical and Computer Engineering of the University of Illinois at Urbana-Champaign, where he is now an assistant professor.

Dr. Chiu was a recipient of the Cal View Teaching Fellow Award, the Regents' Fellowship, the Intel Ph.D. Fellowship at Berkeley, the Foreign Scholar Award at UCLA, the 2004 Outstanding Overseas Student Award and the 2006 Chunhui Award for Foreign Visiting Scholars from China's Ministry of Education. In addition, he received the 2005 Jack Kilby Award from the International Solid-State Circuits Conference (ISSCC), and in 2009, he was a co-recipient of the 46th DAC/ISSCC Student Design Contest Award. He is an IEEE member and an Associate Editor of the IEEE Transactions on Circuits and Systems II: Express Briefs. He was also a member of the Technical Program Committees of the IEEE Custom Integrated Circuits Conference (CICC), the IEEE Asian Solid-State Circuits Conference (A-SSCC), the IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), and the IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). He holds one U.S. patent.

Publications:

  Book:

1. Y. Chiu, Analysis and Design of Pipeline Analog-to-Digital Converters, Springer-Verlag, TBP. ISBN: 0387270396.

  Conference Papers:

2. W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, Y. Chiu, "A 600MS/s 30mW 0.13um CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization," in IEEE International Solid-State Circuits Conference, ISSCC'09, San Francisco, CA, 2009.  Winner of the 46th DAC/ISSCC Student Design Contest

3. H. Li, D.-H. Kwon, and Y. Chiu, "A fast digital adaptive predistortion and loop-delay compensation algorithm for RF power amplifier linearization," in IEEE Power Amplifier Symposium, PAS'09, San Diego, CA, 2009.

4. (Invited) Y. Chiu, "Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters," in 9th IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'08), Beijing, China, 2008.

5. S. Hoyos, B. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, and B. Nikolic, "A 15 MHz-600 MHz, 20 mW, 0.38 mm², fast coarse locking digital DLL in 0.13um CMOS," in 34th IEEE European Solid-State Circuits Conference, ESSCIRC'08, Edinburgh, UK, 2008.

6. B. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, and B. Nikolic, "Background ADC calibration in digital domain," in IEEE Custom Integrated Circuits Conference, CICC'08, San Jose, CA, 2008.

7. D.-H. Kwon, H. Li, and Y. Chiu, "Efficiency and linearity enhancement of CMOS RF power amplifiers using adaptive baseband digital predistortion," in IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT'08), Hsinchu, Taiwan, 2008.

8. R. Tseng, A. S. Poon, and Y. Chiu, "A mixed-signal MIMO beamforming receiver", in IEEE Radio and Wireless Symposium, RWS'08, Orlando, FL, 2008.

9. P. Bhoraskar and Y. Chiu, "A 6.1-mW dual-loop digital DLL with 4.6-ps rms jitter using window-based phase detector," in IEEE Asian Solid-State Circuits Conference, A-SSCC'07, Jeju, Korea, 2007.

10. W. Liu and Y. Chiu, "An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters," in 7th IEEE International Conference on ASIC, ASICON'07, Guilin, China, 2007.

11. P. Huang and Y. Chiu, "A gradient-based digital algorithm for sampling clock skew calibration of SHA-less pipeline ADCs," in IEEE International Symposium on Circuits and Systems, ISCAS'07, New Orleans, LA, 2007.

12. B. Tsang, Y. Chiu, and B. Nikolic, "A 1.2V, 10.8mW, 500kHz DS modulator with 84dB SNDR and 96dB SFDR," in IEEE Symposium on VLSI Circuits, VLSI'06, Honolulu, Hawaii, 2006.

13. (Invited) Y. Chiu, B. Nikolic, and P. R. Gray, "Scaling of analog-to-digital converters into ultra-deep-submicron CMOS," in IEEE Custom Integrated Circuits Conference, CICC'05, San Jose, CA, 2005.

14. Y. Chiu, P. R. Gray, and B. Nikolic, "A 1.8V 14b 10MS/s pipelined ADC in 0.18um CMOS with 99dB SFDR," in IEEE International Solid-State Circuits Conference, ISSCC'04, San Francisco, CA, 2004.

 Recipient of the ISSCC'05 Jack Kilby Award

15. Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband linearization of externally modulated fiber-optic links," in IEEE International Topical Meeting on Microwave Photonics, MWP'98, Princeton, NJ, 1998.

  Journal Articles:

16. H. Li, D.-H. Kwon, D. Chen, and Y. Chiu, "A fast digital predistortion algorithm for radio-frequency power amplifier linearization with loop delay compensation," to appear in IEEE Journal of Selected Topics in Signal Processing.

17. W. Liu and Y. Chiu, "Background digital calibration of successive approximation ADC with adaptive equalization," to appear in Electronics Letters.

18. P. Huang and Y. Chiu, "Calibration of sampling clock skew in SHA-less pipeline ADCs," Electronics Letters, vol. 44, No. 18, pp. 1061-1062, Aug. 2008.

19. R. Tseng, A. S. Poon, and Y. Chiu, "A mixed-signal vector modulator for eigen-beamforming receivers," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, pp. 479-483, May 2008.

20. Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE Journal of Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004.

21. Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, "Least-mean-square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Transactions on Circuits and Systems I, special issue of Advances on Analog-to-Digital and Digital-to-Analog Converters, vol. 51, pp. 38-46, Jan. 2004.

22. Y. Chiu, "Inherently linear capacitor error-averaging techniques for pipelined A/D conversion," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 229-232, March 2000.

23. Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband electronic linearizer for externally modulated analog fiber-optic links," IEEE Journal of Photonics Technology Letters, vol. 11, pp. 48-50, Jan. 1999.

  Invited Conference and Workshop Tutorials/Presentations:

24. Tutorial Speaker, 7th IEEE International Conference on ASIC (ASICON'07), 2007

25. Speaker, Illinois Wireless Systems Symposium (ICWS) and ICWS Circuits Area Open Forum, 2007

26. Speaker, DARPA/MTO TEAM Final PI Review, 2007

27. Short Course Instructor, workshops of 2007 International Microwave Symposium (IMS'07)

28. Tutorial Speaker, 2006 IEEE Asian Solid-State Circuits Conference (A-SSCC'06)

29. Short Course Instructor, 2006 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT'06)

  Conferences, Workshops, and Seminars Organized/Chaired:

30. Session co-chair, 2008 IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'08)

31. Session co-chair, 2008 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-DAT'08)

32. Co-organizer of Circuits Area Open Forum of Illinois Wireless Systems Symposium (ICWS), 2007

33. Session co-chair, 7th IEEE International Conference on ASIC (ASICON'07), 2007

34. Session co-chair, 2006 IEEE Custom Integrated Circuits Conference (CICC'06)

35. Session co-chair, 2006 IEEE Asian Solid-State Circuits Conference (A-SSCC'06)

36. Session chair, 2006 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-DAT'06)

Patent:

1. Y. Chiu, "Improved CMOS gain-boosting scheme using pole-isolation technique," U.S. patent No. 6,177,838.

©  Last modified: 02/18/09