Posted versions here are for personal use only. Copyright is maintained by the authors as well as other copyright holders.

Books



  1. N. Jha and D. Chen, editors, Nanoelectronic Circuit Design, Springer Publishers, 2011. Get a copy.

Monographs



  1. D. Chen, J. Cong, and P. Pan, FPGA Design Automation: A Survey, Foundations and Trends in Electronic Design Automation, NOW Publishers, 137 pages, November 2006.

Book Chapters



  1. D. Chen, Chapter 38: Design Automation for Microelectronics, Handbook of Automation, edited by Shimon Y. Nof, Springer Publishers, August 2009.

  2. S. Chilstedt, C. Dong, and D. Chen, Carbon Nanomaterial Transistors and Circuits, Transistors: Types, Materials, and Applications, edited by Benjamin M. Fitzgerald, Nova Science Publishers, 2010.

  3. C. Dong, S. Chilstedt, and D. Chen, FPCNA: a Carbon Nanotube-Based Programmable Architecture, Nanoelectronic Circuit Design, edited by Niraj Jha and Deming Chen, Springer Publishers, 2011.

JOURNAL PAPERS



  1. Y-Y. Chen, A. Sangai, A. Rogachev, M. Gholipour, and D. Chen, "A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis under Process Variation," submitted to ACM Transactions on Design Automation of Electronic Systems.

  2. H. Zheng, S. T. Gurumani, L. Yang, D. Chen, and K. Rupnow, "High-level Synthesis with Behavioral-level Multi-cycle Path Analysis," submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

  3. M. T. Satria, Y. Liang, K. Rupnow, and D. Chen, "An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization," submitted to IEEE Transactions on Parallel and Distributed Systems.

  4. M. Gholipour, N. Masoumi, Y-Y. Chen, D. Chen, and M. Pourfath, "Asymmetric Gate Schottky-Barrier Graphene Nano-Ribbon FETs for Low Power Design," submitted to IEEE Transactions on Electron Devices.

  5. M. Gholipour, Y-Y. Chen, A. Sangai, N. Masoumi, and D. Chen, "Analytical SPICE-Compatible Model of Schottky-Barrier-type GNRFETs with Performance Analysis," submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

  6. Z. Zhang and D. Chen, "High-Level Synthesis for Low-Power Design," IPSJ Transactions on System LSI Design Methodology. To appear. (Invited)

  7. H. Luo, S. Wei, D. Chen, and D. Guo, "Hybrid Circuit-Switched Network for On-Chip Communication in Large-Scale Chip-Multiprocessors," Journal of Parallel and Distributed Computing. Accepted. To appear.

  8. Y. Liang, H. P. Huynh, K. Rupnow, S. M. Goh, and D. Chen, "Efficient GPU Spatial-Temporal Multitasking," IEEE Transactions on Parallel and Distributed Systems. To appear.

  9. Y. Heo, X-L. Wu, D. Chen, J. Ma, and W-M Hwu, "BLESS: Bloom-filter-based Error Correction Solution for High throughput Sequencing Reads," Bioinformatics, 2014.

  10. T. Yan, Q. Ma, S. Chilstedt, M. D.F. Wong, and D. Chen, "A Routing Algorithm for Graphene Nanoribbon Circuit," ACM Transactions on Design Automation of Electronic Systems - Special Section on Networks on Chip: Architecture, Tools, and Methodologies, Vol. 18, Issue 4, October 2013.

  11. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, and W-M. Hwu, "Efficient Compilation of CUDA Kernels for High-Performance Computing on FPGAs," ACM Transactions on Embedded Computing Systems, Special Issue on Application-Specific Processors, Vol. 13, Issue 2, September 2013.

  12. X-L. Wu, Heo Y, I. El Hajj, W-M. Hwu, D. Chen, and J. Ma. "TIGER: Tiled Iterative Genome Assembler," BMC Bioinformatics, 2012, 13(Suppl 19):S18, 19 December 2012.

  13. L. Wan, C. Dong and D. Chen, "A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance", International Journal of Reconfigurable Computing, Special Issue on High Performance Reconfigurable Computing, Volume 2012 (2012), Article ID 163542, 17 pages, 2012.

  14. L. Wan and D. Chen, "Analysis of Digital Circuit Dynamic Behavior with Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 5, pp. 662-675, May 2012.

  15. Y. Liang, K. Rupnow, Y. Li, D. Min, M. Do, and D. Chen, "High Level Synthesis: Productivity, Performance and Software Constraints", Journal of Electrical and Computer Engineering, Special Issue on ESL Design Methodology, Volume 2012 (2012), Article ID 649057, 14 pages, 2012.

  16. D. Chen, J. Cong, C. Dong, L. He, F. Li, and C. Peng, "Technology Mapping and Clustering for FPGA Architectures with Dual Supply Voltages," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 11, pp. 1709-1722, Nov. 2010.

  17. G. Lucas, C. Dong, and D. Chen, "Variation-Aware Placement with Multi-cycle Statistical Timing Analysis for FPGAs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 11, pp. 1818-1822, Nov. 2010.

  18. S. Akram, A. Papakonstantinou, R. Kumar, and D. Chen, "Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects," Journal of Reconfigurable Computing, Vol. 2010, Article ID 205852, 22 pages, 2010.

  19. Q. Dinh, D. Chen, and D. F. Wong, "A Routing Approach to Reduce Glitches in Low Power FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, pp. 235-240, February 2010.

  20. D. Chen, J. Cong, Y. Fan, and L. Wan, "LOPASS: A Low-Power Architectural Synthesis System for FPGAs with Interconnect Estimation and Optimization", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 4, pp. 564-577, April 2010.

  21. D. Chen and S. Cromar, "An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power", Journal of Low Power Electronics, Vol. 5, No. 4, pp. 454-463, December 2009.

  22. S. Chilstedt, C. Dong, and D. Chen, "Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture", International Journal of Parallel Programming (IJPP), Special Issue on Nano/Bio-Inspired Applications, Architectures and Software, Vol. 37, Issue 4, pp. 389-416, August 2009.

  23. H. Li, D. H. Kwon, D. Chen, and Y. Chiu, "A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization with Loop Delay Compensation," IEEE Journal of Selected Topics in Signal Processing, Special Issue on: DSP Techniques for RF/Analog Circuit Impairments, Vol. 3, No. 3, pp.374-383, June 2009.

  24. L. Cheng, D. Chen, and D.F. Wong, "DDBDD: Delay-Driven BDD Synthesis for FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 7, pp.1203-1213, July 2008.

  25. L. Cheng, D. Chen, and D.F. Wong, "A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction," ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 2, Article 34, pp. 1-15, April 2008.

  26. C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 54, Issue 11, pp. 2489-2501, November 2007.

  27. D. Chen, J. Cong, and J. Xu, "Optimal Simultaneous Module and Multi-Voltage Assignment for Low-Power," ACM Transactions on Design Automation of Electronic Systems, vol. 11, Issue 2, pp. 362-386, April 2006.

  28. F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power Modeling and Characteristics of Field Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, Issue 11, pp. 1712-1724, November 2005. (One of the most-downloaded papers from TCAD ranked by CEDA)

  29. D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1424-1431, October 2003.

CONFERENCE PAPERS



  1. W. Zuo, H. Zheng, and D. Chen, "New Solutions for System-Level and High-Level Synthesis," Proceedings of IEEE International Symposium on Integrated Circuits, December 2014. (Invited)

  2. R. Mancuso, P. Srivastava, D. Chen, and M. Caccamo, "A Hardware Architecture to Deploy Complex Multiprocessor Scheduling Algorithms," Proceedings of IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, August 2014.

  3. Y. Liang and D. Chen, "New Algorithms for Computation Acceleration for Large-scale Smart Grids," Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology, October 2014. (Invited)

  4. J. Wang, A. Dhar, D. Chen, Y. Liang, Y. Wang, and B. Guo, "Workload Allocation and Thread Structure Optimization for MapReduce on GPUs," Proceedings of SRC Technical Conference (TECHCON), September 2014.

  5. Y. Liang and D. Chen, "ClusRed: Clustering and Network Reduction-based Probabilistic Optimal Power Flow Analysis for Large-scale Smart Grids," Proceedings of IEEE/ACM Design Automation Conference, June 2014.

  6. C.-H. Lin, L. Wan, and D. Chen, "C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs," Proceedings of IEEE/ACM Design Automation Conference, June 2014.

  7. S. Gurumani, J. Tolar, Y. Chen, Y. Liang, K. Rupnow, and D. Chen, "Integrated CUDA-to-FPGA Synthesis with Network-on-Chip," Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014.

  8. M. Gholipour, Y-Y, Chen, A. Sangai, and D. Chen, "Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling," Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2014.

  9. H. Zheng, S. Gurumani, K. Rupnow, and D. Chen, "Fast and Effective Placement and Routing Directed High-Level Synthesis for FPGAs," Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2014.

  10. Y. Liang and D. Chen, "Fast Large-Scale Optimal Power Flow Analysis for Smart Grid through Network Reduction," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2014.

  11. S. T. C. Konigsmark, L. Hwang, D. Chen, and D. F. Wong, "CNPUF: A Carbon Nanotube-based Physically Unclonable Function for Secure Low-Energy Hardware Design," ProceediEEE/ACM Asia and South Pacific Design Automation Conference, January 2014.

  12. X. Xie, Y. Liang, G. Sun, and D. Chen, "An Efficient Compiler Framework for Cache Bypassing on GPUs," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2013.

  13. W. Zuo, P. Li, D. Chen, L-N. Pouchet, S. Zhong, and J. Cong, "Improving Polyhedral Code Generation for High-Level Synthesis," Proceedings of IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, September 2013. (Best Paper Award)

  14. Y-Y. Chen, A. Sangai, M. Gholipour, and D. Chen, "Graphene Nano-Ribbon Field-Effect Transistors as Future Low-Power Devices," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, September 2013. (Invited)

  15. H. Zheng, S. Gurumani, L. Yang, D. Chen, K. Rupnow, "High-level Synthesis with Behavioral level Multi-Cycle Path Analysis," Proceedings of IEEE International Conference on Field Programmable Logic and Applications, September, 2013.

  16. Y-Y. Chen, A. Sangai, M. Gholipour, and D. Chen, "Schottky-Barrier-Type Graphene Nano-Ribbon Field-Effect Transistors: A Study on Compact Modeling, Process Variation, and Circuit Performance," Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures, July 2013.

  17. A. Papakonstantinou, D. Chen, W.M. Hwu, J. Cong, and Y. Liang, "Throughput-oriented Kernel Porting onto FPGAs," Proceedings of IEEE/ACM Design Automation Conference, June 2013.

  18. Y-Y. Chen, A. Rogachev, A. Sangai, G. Iannaccone, G. Fiori, and D. Chen, "A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis Under Process Variation," Proceedings of IEEE/ACM Design, Automation & Test in Europe, March 2013.

  19. Y. Liang, H. P. Huynh, K. Rupnow, R. Goh, and D. Chen, "Efficient Concurrent Kernel Execution on GPUs," Proceedings of Workshop on SoCs, Heterogeneous Architectures and Workloads, February, 2013.

  20. W. Zuo, Y. Liang, K. Rupnow, P. Li, D. Chen, and J. Cong, "Improving High Level Synthesis Optimization Opportunity Through Polyhedral Transformations," Proceedings of ACM International Symposium on Field Programmable Gate Arrays, February 2013.

  21. Y. Liang, Z. Cui, K. Rupnow, and D. Chen, "Register and Thread Structure Optimization for GPUs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2013.

  22. S. Gurumani, K. Rupnow, Y. Liang, H. Cholakkail, and D. Chen, "High Level Synthesis of Multiple Dependent CUDA Kernels for FPGAs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2013. (Invited)

  23. Z. Zhang and D. Chen, "Challenges and Opportunities of ESL Design Automation," Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology, October 2012. (Invited)

  24. H. Luo, S. Wei, D. Chen, and D. Guo, "Hybrid Circuit-Switched NOC for Low Cost On-chip Communication," Proceedings of IEEE International Conference on Anti-Counterfeiting, Security and Identification, August 2012.

  25. L. Wan and D. Chen, "CCP: Common Case Promotion for Improved Timing Error Resilience with Energy Efficiency," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, July 2012.

  26. W. Huang, Y. Quan, and D. Chen, "Improving Broadcast Efficiency in Wireless Sensor Network Time Synchronization Protocols," Proceedings of IEEE/ACM International Workshop on System Level Interconnect Prediction, June 2012.

  27. S. Zhao, S. Ahmed, Y. Liang, K. Rupnow, D. Chen and D. L. Jones, "A Real-Time 3D Sound Localization System with Miniature Microphone Array for Virtual Reality," Proceedings of IEEE Conference on Industrial Electronics and Applications, July 2012.

  28. Z. Cui, Y. Liang, K. Rupnow, and D. Chen, "An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization," Proceedings of IEEE International Parallel & Distributed Processing Symposium, May 2012.

  29. K. S. Yim, V. Sidea, Z. Kalbarczyk, D. Chen, and R. K. Iyer, "A Fault-Tolerant Programmable Voter for Software-Based N-Modular Redundancy," Proceedings of the IEEE Aerospace Conference, March 2012.

  30. Y. Liang, Z. Cui, S. Zhao, K. Rupnow, Y. Zhang, D. L. Jones, and D. Chen, "Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs," Proceedings of IEEE/ACM Design, Automation & Test in Europe, Mar. 2012.

  31. K. Rupnow, Y. Liang, Y. Li, D. Min, M. Do, and D. Chen, "High Level Synthesis of Stereo Matching: Productivity, Performance, and Software Constraints," Proceedings of IEEE International Conference on Field-Programmable Technology, December 2011. (Best Paper Nomination)

  32. K. Rupnow, Y. Liang, Y. Li, and D. Chen, "A Study of High-Level Synthesis: Promises and Challenges," Proceedings of IEEE International Conference on ASIC, October 2011. (Invited)

  33. A. Rogachev, L. Wan and D. Chen, "Temperature Aware Statistical Static Timing Analysis," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2011.

  34. A. Papakonstantinou, D. Chen, and W.M. Hwu, "A Code Optimization Framework for Performance Portability of Parallel Kernels Across GPUs and Custom Accelerators", SRC Technical Conference (TECHCON), Sept. 2011.

  35. S. Liu, A. Papakonstantinou, H. Wang, and D. Chen, "Real-time Object Tracking System on FPGAs," Proceedings of Symposium on Application Accelerators in High Performance Computing, July 2011. (Best Paper Award)

  36. C. Dong, C. Chen, S. Mitra, and D. Chen, "Architecture and Performance Evaluation of 3D CMOS-NEM FPGA," Proceedings of IEEE/ACM International Workshop on System Level Interconnect Prediction, June 2011.

  37. A. Papakonstantinou, Y. Liang, J. Stratton, K. Gururaj, D. Chen, W.M. Hwu and J. Cong, "Multilevel Granularity Parallelism Synthesis on FPGAs," Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2011. (Best Paper Award)

  38. C. Peng, C. Dong, and D. Chen, "SETmap: A Soft Error Tolerant Mapping Algorithm for FPGA Designs with Low Power," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2011.

  39. T. Yan, Q. Ma, S. Chilstedt, D. F. Wong, and D. Chen, "Routing with Graphene Nanoribbons," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2011.

  40. G. Lucas and D. Chen, "Variation-Aware Layout-Driven Scheduling for Performance Yield Optimization," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2010.

  41. L. Wan and D. Chen, "Analysis of Circuit Dynamic Behavior with Timed Ternary Decision Diagram," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2010.

  42. Q. Dinh, D. Chen, and D.F. Wong, "BDD-Based Circuit Restructuring for Reducing Dynamic Power," Proceedings of IEEE International Conference on Computer Design, October 2010.

  43. Y. Chen, C. Dong, and D. Chen, "Clock Tree Synthesis under Aggressive Buffer Insertion," Proceedings of IEEE/ACM Design Automation Conference, June 2010.

  44. G. Lucas, C. Dong, and D. Chen, "Variation-Aware Placement for FPGAs with Multi-cycle Statistical Timing Analysis", Proceedings of ACM/SIGDA International Symposium on FPGA, February 2010.

  45. Q. Dinh, D. Chen, and D.F. Wong "Dynamic Power Estimation for Deep Submicron Circuits with Process Variation", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2010.

  46. L. Wan and D. Chen, "DynaTune: Circuit-Level Optimization for Timing Speculation Considering Dynamic Path Behavior", Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2009.

  47. C. He, A. Papakonstantinou, and D. Chen, "A Novel SoC Architecture on FPGA for Ultra Fast Face Detection", Proceedings of IEEE International Conference on Computer Design, October 2009.

  48. L. Wan, C. Dong, and D. Chen, "A New Coarse-Grained Reconfigurable Architecture with Fast Data Relay and Its Compilation Flow," Proceedings of Symposium on Application Accelerators in HPC, July 2009.

  49. S. Akram, R. Kumar, and D. Chen, "Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects," Proceedings of IEEE Symposium on Application Specific Processors, July 2009.

  50. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, and W.M. Hwu, "FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs," Proceedings of IEEE Symposium on Application Specific Processors, July 2009. (Best Paper Award)

  51. S. Cromar, J. Lee, and D. Chen, "FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation," Proceedings of IEEE/ACM Design Automation Conference, July 2009.

  52. C. Dong, S. Chilstedt, and D. Chen, "Variation Aware Routing for Three-Dimensional FPGAs," Proceedings of IEEE Computer Society Annual Symposium on VLSI, May 2009.

  53. C. Dong, S. Chilstedt, and D. Chen, "Reconfigurable Circuit Design with Nanomaterials," Proceedings of Design, Automation and Test in Europe, April 2009. (Invited)

  54. Q. Dinh, D. Chen, and D.F. Wong, "A Routing Approach to Reduce Glitches in Low Power FPGAs," Proceedings of IEEE/ACM International Symposium on Physical Design, March 2009.

  55. C. Dong, S. Chilstedt, and D. Chen, "FPCNA: Field Programmable Carbon Nanotube Array," Proceedings of ACM/SIGDA International Symposium on FPGA, February 2009.

  56. B. Greskamp, L. Wan, R. Karpuzcu, J. Cook, J. Torrellas, D. Chen, and C. Zilles "BlueShift: Designing Processors for Timing Speculation from the Ground Up," Proceedings of IEEE International Symposium on High-Performance Computer Architecture, February 2009.

  57. G. Lucas, S. Cromar, and D. Chen, "FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2009. (Best Paper Award)

  58. A. Papakonstantinou, Y. Kifle, G. Lucas, and D. Chen, "MP3 decoding on FPGA: A case study for floating point acceleration," Proceedings of Reconfigurable Systems Summer Institute, Urbana, IL, July 2008.

  59. A. Papakonstantinou, D. Chen, and W.M. Hwu, "Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor," Proceedings of IEEE Symposium on Application Specific Processors, June 2008.

  60. Q. Dinh, D. Chen, and D.F. Wong, "Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing," Proceedings of ACM/SIGDA International Symposium on FPGA, February 2008.

  61. S. Akram, S. Cromar, G. Lucas, A. Papakonstantinou, and D. Chen, "VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2008. (Invited)

  62. C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "Performance and Power Evaluation of a 3D CMOS/Nanomaterial Reconfigurable Architecture," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007.

  63. L. Cheng, D. Chen, D.F. Wong, M. Hutton, and J. Govig, "Timing Constraint-driven Technology Mapping for FPGAs Considering False Paths and Multi-Clock Domains," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007.

  64. Q. Dinh, Y. Bresler, and D. Chen, "Hardware Acceleration for Sparse Fourier Image Reconstruction," Proceedings of IEEE International Conference on ASIC, Oct. 2007. (Invited)

  65. L. Cheng, D. Chen, and D.F. Wong, "GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches," Proceedings of IEEE/ACM Design Automation Conference, Jun. 2007.

  66. L. Cheng, D. Chen, and D.F. Wong, "DDBDD: Delay-Driven BDD Synthesis for FPGAs," Proceedings of IEEE/ACM Design Automation Conference, Jun. 2007.

  67. D. Chen, J. Cong, Y. Fan and Z. Zhang, "High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Jan. 2007.

  68. L. Cheng, L. Deng, D. Chen, and D.F. Wong, "A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction," Proceedings of IEEE/ACM Design Automation Conference, July 2006.

  69. J. Lin, D. Chen, and J. Cong, "Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization," Proceedings of IEEE/ACM Design Automation Conference, July 2006.

  70. D. Chen, J. Cong, Y. Fan, and J. Xu, "Optimality Study of Resource Binding with Multi-Vdds," Proceedings of IEEE/ACM Design Automation Conference, July 2006.

  71. D. Chen, J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "xPilot: A Platform-Based Behavioral Synthesis System," Proceedings of SRC Techcon Conference, October 2005.

  72. D. Chen, J. Cong, and J. Xu, "Optimal Module and Voltage Assignment for Low-Power," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, pp. 850-855, January 2005.

  73. D. Chen and J. Cong, "DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, pp. 752-759, November 2004.

  74. D. Chen and J. Cong, "Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, Newport Beach, California, pp. 70-73, August 2004.

  75. D. Chen, J. Cong, F. Li, and L. He, "Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages," Proceedings of ACM International Symposiumon Field-Programmable Gate Arrays, Monterey, California, pp. 109-117, February 2004.

  76. D. Chen and J. Cong, "Register Binding and Port Assignment for Multiplexer Optimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp. 68-73, January 2004.

  77. D. Chen, J. Cong, and Y. Fan, "Low-Power High-Level Synthesis for FPGA Architectures," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design, Seoul, Korea, pp. 134-139, August 2003.

  78. F. Li, D. Chen, L. He, and J. Cong, "Architecture Evaluation for Power-Efficient FPGAs," Proceedings of ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 175-184, February 2003.

  79. D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architectures," Proceedings of ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 39-47, February 2001.

  80. D. Chen, R. Colwell, H. Gelman, P. K. Chrysanthis, and D. Mosse, "A Framework for Experimenting with QoS for Multimedia Services," Proceedings of International Conference on Multimedia Computing and Networking, San Jose, California, January 1996.

Other Workshop Papers, Poster Papers or Online Publications



  1. Y-Y Chen, A. Sangai, M. Gholipour, and D. Chen, "Effects of Process Variation on the Circuit-Level Performance of Graphene Nano-Ribbon Field-Effect Transistors," Workshop on Variability Modeling and Characterization, November 2013.

  2. K. Rupnow, Y. Liang, D. Min, M. Do and D. Chen, "Mobile 3D Vision - Algorithm and Platform Challenges," FPL 2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures, 2011.

  3. D. Chen, S. Chilstedt, C. Dong, and E. Pop, "What Everyone Needs to Know about Carbon-Based Nanocircuits," Online Knowledge Center, Topic: Back-End, Sub-topic: New Technologies and Directions, IEEE/ACM Design Automation Conference, 2010. (Invited)

  4. L. Wan and D. Chen, "Circuit Level Dynamic Behavior Analysis through Timed Ternary Decision Diagram," Proceedings of International Workshop on Logic & Synthesis, June 2010.

  5. Z. Zhang and D. Chen, "Challenges and Opportunities of ESL Design Automation", IEEE Electronic Design Processes Symposium, April 2010. (Invited)

  6. A. Papakonstantinou, K. Gururaj, J. Stratton, D. Chen, J. Cong, and W.M. Hwu, "High-Performance CUDA Kernel Execution on FPGAs," International Conference on Supercomputing, June 2009. (Two-page extended abstract.)

  7. C. Dong, S. Chilstedt, and D. Chen, "Variation Aware Routing for Three-Dimensional FPGAs," Workshop on 3D Integration and Interconnect-Centric Architectures, Feb. 2009. (A later version with the same title appeared in IEEE Computer Society Annual Symposium on VLSI, May 2009.)